Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features

ABSTRACT

Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. patent application Ser. No.13/864,344, entitled “COMBINING CUT MASK LITHOGRAPHY AND CONVENTIONALLITHOGRAPHY TO ACHIEVE SUB-THRESHOLD PATTERN FEATURES,” filed on Apr.17, 2013, the disclosure of which is expressly incorporated by referenceherein in its entirety.

BACKGROUND

1. Field

Aspects of the present disclosure relate generally to semiconductordevice design and manufacture, and more particularly to lithographicprocesses used in the semiconductor manufacturing process.

2. Background

Photolithographic technology plays an important role in the manufactureof integrated circuits (ICs) (also referred to as semiconductor chips.)Improvements in lithography have enabled the printing of smallerfeatures of integrated circuits. This, in turn, has allowed forproduction of more densely populated integrated circuits and morepowerful and cost-effective semiconductor devices.

However, there are times when even the most advanced techniques, e.g.,use of laser light or lower wavelength light for exposure of the maskgeometries, still have limitations that are unable to achieve specificdesigns.

Lithographic processes are often referred to by the smallest feature,which may be the line width, spacing between lines, or the distance fromline tip to line tip. The smallest feature in a given lithographicprocess is often referred to as the “threshold,” in that the thresholddistance is the smallest distance that can be produced using a certainlithographic technique. Currently, there are “20 nanometer” or “30nanometer” technologies, which indicate that the smallest feature, whichcan be the width of a trace on a semiconductor device, is used as thename for that technology. So, a 20 nm process can produce a feature assmall as 20 nm.

When small features are being produced, there is often a need to createa contact pad or other sub-portion of a feature that is smaller than theprocess limitation. This may only happen in a few places on a chip.Because such features cannot be consistently manufactured, the chiplayout is redesigned to accommodate these limitations, which takes upadditional semiconductor real estate and increases costs of the ICs.

It can be seen, then, that there is a need in the art to achievesub-threshold features within a semiconductor chip.

SUMMARY

The present disclosure describes methods and apparatuses for fabricatingfeatures on a semiconductor chip that are smaller than the threshold ofthe lithography used to create the chip.

A method of making a semiconductor device in accordance with one aspectof the present disclosure includes patterning a first portion of afeature and a second portion of the feature separated by a firstpredetermined distance. The method further includes patterning the firstportion with a cut mask to form a first sub-portion and a secondsub-portion. A dimension of the first sub-portion is less than adimension of a second predetermined distance.

A feature of a semiconductor device in accordance with another aspect ofthe present disclosure includes a first portion. The feature furtherincludes a second portion having a dimension less than a lithographicresolution of the first portion.

A computer program product configured for making a semiconductor devicein accordance with another aspect of the present disclosure includes anon-transitory computer-readable medium having non-transitory programcode recorded thereon. The non-transitory program code includes programcode to pattern a first portion of a feature and a second portion of thefeature separated by a first predetermined distance. The non-transitoryprogram code further includes program code to pattern the first portionwith a cut mask to form a first sub-portion and a second sub-portion. Adimension of the first sub-portion is less than a dimension of a secondpredetermined distance.

In yet another aspect, an apparatus for making a semiconductor devicehas means for patterning a first portion of a feature and a secondportion of the feature separated by a first predetermined distance. Theapparatus also has means for patterning the first portion to form afirst sub-portion and a second sub-portion. A dimension of the firstsub-portion is less than a dimension of a second predetermined distance.

This has outlined, rather broadly, the features and technical advantagesof the present disclosure in order that the detailed description thatfollows may be better understood. Additional features and advantages ofthe disclosure will be described below. It should be appreciated bythose skilled in the art that this disclosure may be readily utilized asa basis for modifying or designing other structures for carrying out thesame purposes of the present disclosure. It should also be realized bythose skilled in the art that such equivalent constructions do notdepart from the teachings of the disclosure as set forth in the appendedclaims. The novel features, which are believed to be characteristic ofthe disclosure, both as to its organization and method of operation,together with further objects and advantages, will be better understoodfrom the following description when considered in connection with theaccompanying figures. It is to be expressly understood, however, thateach of the figures is provided for the purpose of illustration anddescription only and is not intended as a definition of the limits ofthe present disclosure.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure, referenceis now made to the following description taken in conjunction with theaccompanying drawings.

FIGS. 1A-1E illustrate a conventional build-up of a semiconductordevice.

FIG. 2A illustrates a top view of features created on a semiconductorsubstrate in accordance with an aspect of the present disclosure.

FIG. 2B illustrates use of a cut mask according to one aspect of thedisclosure.

FIG. 2C illustrates a top view of features created on a semiconductorsubstrate in accordance with an aspect of the present disclosure.

FIG. 3 is a flow chart illustrating an example of a method according toone aspect of the disclosure.

FIG. 4 is a block diagram showing an exemplary wireless communicationsystem in which an aspect of the disclosure may be advantageouslyemployed.

FIG. 5 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of a semiconductor component.

DETAILED DESCRIPTION

The detailed description set forth below, in connection with theappended drawings, is intended as a description of variousconfigurations and is not intended to represent the only configurationsin which the concepts described herein may be practiced. The detaileddescription includes specific details for the purpose of providing athorough understanding of the various concepts. However, it will beapparent to those skilled in the art that these concepts may bepracticed without these specific details. In some instances, well-knownstructures and components are shown in block diagram form in order toavoid obscuring such concepts. As described herein, the use of the term“and/or” is intended to represent an “inclusive OR”, and the use of theterm “or” is intended to represent an “exclusive OR”.

FIG. 1A illustrates a side view of a substrate 100. The substrate 100can be silicon, or can be other semiconductor materials, such as galliumarsenide (GaAs), gallium nitride (GaN), other single-element or compoundsemiconductors, or even glass, sapphire, quartz, sapphire,high-resistivity silicon, or other like semiconductor materials withoutdeparting from the scope of the present disclosure. The substrate 100may also have dopant wells, or have other layers of device film orpatterns already present. Such wells and layers are not shown in FIGS.1A-1E for clarity.

To fabricate patterns on the substrate 100, a layer of photoresist 102is applied to the substrate 100 as shown in FIG. 1B. The photoresist 102can be applied via spin techniques or by coating the substrate 100 witha spray or misting of photoresist 102. Photoresist 102 is usually alight-sensitive polymer that, after exposure to certain wavelengths oflight, can be selectively removed from substrate 100.

FIG. 1C shows a mask 104 placed on the photoresist 102. The mask 104 hasfeatures 106, 108, and 110, and spacings 112 and 114. As an example, andnot by way of limitation, the mask 104 is shown where feature 106 islarger than features 108 and 110, and spacing 114 is larger than spacing112. Also as an example, and not by way of limitation, features 108 and110 are at the threshold of the lithographic technique being used inconjunction with the mask 104. Thus, these features 108 and 110 are, forpurposes of the explanation of the present disclosure, the smallestfeatures that can be transferred to the substrate 100 through thephotoresist 102. Although shown as creating features 106, 108, 110 andspacings 112 and 114 with a mask, such features can be patterned, orotherwise made using direct exposure of the photoresist with alaser/light source, or through other means, without departing from thescope of the present disclosure.

Also as shown in FIG. 1C, for purposes of discussion, spacing 112 issmaller than the threshold of the lithographic technique used inconjunction with the mask 104. Light 116 will selectively expose thephotoresist 102 through the features 106, 108, 110 and spacings 112 and114, which will allow for selective removal of the photoresist 102 andprocessing of the substrate 100. FIG. 1D illustrates a top view of themask 104, where the light 116 would be shining onto the page from theperspective of the reader.

FIG. 1E illustrates the photoresist layer 102 after exposure to thelight 116 and removal of the exposed photoresist. Features 106, 108, and110, and spacings 112 and 114, are shown in phantom to illustrate theireffect on the photoresist 102 exposure. The wavelength of light 116, aswell as the mask 104 or other techniques used to expose the photoresistlayer 102 can contribute to the lithographic resolution of the processdescribed in FIGS. 1A-1E.

Exposed areas 120 are shown where the photoresist was fully exposed tolight 116. The exposed areas 120 are now available for furtherprocessing of the substrate 100. For example, the exposed areas 120 cannow be metallized, or have dopants implanted, as desired within thedesign of the devices to be placed on substrate 100.

Although the design of the mask 104 also used spacing 112, which wasbelow the threshold feature size of mask 104, unexposed area 122 cannotbe processed as desired. Thus, the unexposed area, which is designed toreceive similar processing as exposed areas 120, will not receive thatprocessing, or will receive incomplete processing, because thephotoresist 102 was not fully exposed in the spacing 112. This resultsin the substrate 100 having defects in the overall circuitry because theunexposed area 122 has not received the proper processing due to thefeature size of the spacing 112.

As additional masks 104 are used, or other lithographic processes areemployed to further pattern or process the substrate 100, the substrate100 may have additional problems because the unexposed area 122 mayaffect the additional processing. Moreover, the other masks 104 may havesimilar problems.

Although the “sub-threshold” issue illustrated in FIG. 1A-1E is relatedto a sub-threshold spacing 112 between features 108 and 110, thesub-threshold issue of the present disclosure can also be related toother sub-threshold feature sizes, including feature width, e.g., width214, feature length, feature tip-to-tip space, and other featuredimensions.

The present disclosure allows for the fabrication of sub-thresholdfeatures, which may include a sub-threshold line length.

FIGS. 2A-C illustrates a top view of features created on a semiconductorsubstrate in accordance with an aspect of the present disclosure.

To manufacture semiconductor device features, conventional lithographictechniques, as described with respect to FIGS. 1A-1E, are used toprovide openings in the photoresist 102 for diffusion, contact pads,metallization, etc. Initially, lithographic feature sizes were in the 1micron range, but as devices and device physics have been betterutilized, conventional lithography techniques are currently in the 30nanometer range (with sizes continuing to decrease). This creates higherdensity chips.

Nevertheless, it is often desirable to create some features that aresmaller than the lithographic feature limits of the technology beingused to create the semiconductor chip. The present disclosure, in one ormore aspects, enables creation of features on the chip that are smallerthan the “conventional” lithographic thresholds used to create the chipfeatures.

FIG. 2A illustrates an aspect of the present disclosure.

Conventional lithographic techniques are used on the chip 200 to creategeometric areas, such as feature lines 202-210 and diffusion region 212.The feature lines 202-210, which may be a local interconnect or localinterconnects for transistors, other active devices, other passivedevices, or for diffusion or other metallization regions, are made atthe lithographic resolution (e.g., 20 nm) of the mask 104 and theexposure process described with respect to FIGS. 1A-1E, such that thewidths 214-218 can be at the resolution of the lithographic process. Sofor example, and not by way of limitation, the widths 214-218 in a 20 nmlithographic process are approximately 20 nm. The actual widths 214-218will vary slightly because of process variations, but are considered tobe at the threshold of lithographic reproduction because smaller designwidths cannot be consistently reproduced in such a process, and resultin unexposed areas 122, as shown in FIG. 1E. For a small design width of20 nm, the threshold for a line length can be in the range of 80-100 nm.

Of course, the widths 214-218 can be a larger value than thelithographic resolution of the processes being used with mask 104, whichis shown in FIG. 2A as the width 220 of the feature line 202 and thewidth 222 of the diffusion region 212.

There are occasions in chip design when a dimension of a portion of afeature 202-210 is desired to be less than the lithographic resolutionof the remainder of the chip. Rather than using a process that hasgreater resolution for the entire chip for these occasions, because thatprocess may be more expensive, more time consuming, and result inpossibly lower yields for chip manufacture, the present disclosurecombines a low resolution process with a separate mask that allows foreven lower resolution features.

So, for example, and not by way of limitation, the feature 208 may bedesigned to have a small portion that is used for a point contact,capacitor, or other circuit device or operation. The length of the smallportion is smaller than the lithographic resolution of the remainder ofthe feature lines 202-210. FIG. 2B illustrates an aspect of the presentdisclosure that creates such a portion.

FIG. 2B illustrates a second mask feature 224, called a “cut mask”feature 224 to cut one of the feature lines 208, into two segments,feature 208 and feature 226. By proper placement of the cut mask feature224, which may also be limited by the lithographic resolution similar tothat of the original mask 104, (e.g., the length 230 of the “cut mask”feature 224 may be the same as that of the mask 104 that created thefeatures 202-210) the size of the feature 226 can be selected such thatthe length 228 is less than the lithographic length resolution of themask used to create feature 208 or the lithographic space resolution ofthe mask used to create the feature 224. By setting the location of thefeature 224, and, if desired, the width of the features 208 and 224, thelength 228 of the feature 226 can be a sub-threshold dimension (i.e.,smaller than the lithographic length resolution), which allows for evendenser connections and device packing. FIG. 2C illustrates the removalof the section of the feature 208, and the separation of the feature 226in the area 232.

The cut mask feature 224 may have a different resolution or a differentpitch limit, i.e., the dimension of the feature 224 from left to rightas seen in FIG. 2B, than the original mask 104. Further, the cut maskfeature 224 can be created by a separate mask, or can be created usingother photolithographic techniques, without departing from the scope ofthe present disclosure. However, the feature 226 has a length smallerthan the lithographic length resolution than either mask. Further, thecut mask feature 224 and cut mask process may be performed usingpatterning, as through a metallized layer or through other semiconductoror photoresist layers.

So, for example, feature 210 and feature 208 may be patterned as a firstportion and a second portion of a single feature, and they may beseparated by a predetermined distance 216. The predetermined distance216 may be a line tip to tip space, a line space, or a line lengthresolution of a lithographic process having a specified widthresolution.

As shown in FIG. 2C, the feature 208 may be patterned with a cut mask orin other ways to form a first sub-portion 226 and a second sub-portion228 in which a dimension 228 of the first sub-portion 226 is less than adimension of the predetermined distance 216. Again, the predetermineddistance 216, or spacing 216, may be a line tip to tip space, a linespace, or a line length resolution of a lithographic process having aspecified width resolution.

As such, the cut mask feature 224 may be obtained via patterning thefeatures 202-210 and then patterning the cut mask feature 224 to form anetch block region at feature 224 site. In such a way, the cut mask is inreality a “block mask”. Any combination of patterning, etching, or otherlithographic techniques may be used without departing from the scope ofthe present disclosure.

The top end of the feature 226 may have some curvature rather than beingstraight. Further, the bottom end of the feature 226 is straight due tothe cut mask. Such characteristics of the feature 226 and/or the feature208 can be detected using tunneling electron microscopy or scanningelectron microscopy.

FIG. 3 is a flow chart illustrating an example of a method according toone aspect of the disclosure.

As seen in a flowchart 300, at block 302, a first portion of a featureand a second portion of the feature are patterned. The features (e.g.,portions of the local interconnects) are separated by a firstpredetermined distance. The first predetermined distance can be a linetip to tip space or a line space. In block 304, the first portion ispatterned with a cut mask to form a first sub-portion (e.g., contact)and a second sub-portion. A dimension of the first sub-portion is lessthan a dimension of a second predetermined distance. The secondpredetermined distance can be a line length resolution of a lithographicprocess having a specified width resolution.

The method may also include depositing conductive material on the firstsub-portion and the second sub-portion. After all of the patterning,etching may occur to create the features and contacts. For example, theconductive material deposited on the first sub-portion and the secondsub-portion may be etched to form contact structures. The firstpredetermined distance may a lithographic resolution of a first maskused to pattern the first portion and the second portion. In addition,the second predetermined distance may be the lithographic resolution ofa second mask used to pattern the first sub-portion and the secondsub-portion.

According to a further aspect of the present disclosure, an apparatusfor making a semiconductor device has means for patterning a firstportion of a feature and a second portion of the feature separated by afirst predetermined distance. The apparatus also has means forpatterning the first portion to form a first sub-portion and a secondsub-portion. The means for patterning the first portion and the secondportion may be the lithographic mask 208, 210. The means for patterningthe first sub-portion and the second sub-portion may be the cut mask224. In another aspect, the aforementioned means may be any module orany apparatus configured to perform the functions recited by theaforementioned means.

FIG. 4 is a block diagram showing an exemplary wireless communicationsystem 400 in which an aspect of the disclosure may be advantageouslyemployed. For purposes of illustration, FIG. 4 shows three remote units420, 430, and 450 and two base stations 440. It will be recognized thatwireless communication systems may have many more remote units and basestations. Remote units 420, 430, and 450 include IC devices 425A, 425C,and 425B, which include the disclosed sub threshold features. It will berecognized that any device containing an IC may also include the subthreshold features disclosed here, including the base stations,switching devices, and network equipment. FIG. 4 shows forward linksignals 480 from the two base stations 440 to the remote units 420, 430,and 450 and reverse link signals 490 from the remote units 420, 430, and450 to the two base stations 440.

In FIG. 4, one of the remote units 420 is shown as a mobile telephone,one of the remote units 430 is shown as a portable computer, and one ofthe remote units 450 is shown as a fixed location remote unit in awireless local loop system. For example, a remote unit may be a mobilephone, a hand-held personal communication systems (PCS) unit, a portabledata unit such as a personal data assistant, a GPS enabled device, anavigation device, a set top box, a music player, a video player, anentertainment unit, a fixed location data unit such as a meter readingequipment, or any other device that stores or retrieves data or computerinstructions, or any combination thereof. Although FIG. 4 illustratesremote units according to the teachings of the disclosure, thedisclosure is not limited to these exemplary illustrated units. Aspectsof the disclosure may be suitably employed in any device, which includesintegrated circuits (ICs) having sub threshold features.

FIG. 5 is a block diagram illustrating a design workstation used forcircuit, layout, and logic design of a semiconductor component, such ascircuitry having sub threshold features as disclosed above. A designworkstation 500 includes a hard disk 501 containing operating systemsoftware, support files, and design software such as Cadence or OrCAD.The design workstation 500 also includes a display 502 to facilitate acircuit design 510 or a semiconductor component 512 such as thedisclosed sub threshold features. A storage medium 504 is provided fortangibly storing the circuit design 510 or the semiconductor component512. The circuit design 510 or the semiconductor component 512 may bestored on the storage medium 504 in a file format such as GDSII orGERBER. The storage medium 504 may be a CD-ROM, DVD, hard disk, flashmemory, or other appropriate device. Furthermore, the design workstation500 includes a drive apparatus 503 for accepting input from or writingoutput to the storage medium 504.

Data recorded on the storage medium 504 may specify logic circuitconfigurations, pattern data for photolithography masks, or mask patterndata for serial write tools such as electron beam lithography. The datamay further include logic verification data such as timing diagrams ornet circuits associated with logic simulations. Providing data on thestorage medium 504 facilitates the design of the circuit design 510 orthe semiconductor component 512 by decreasing the number of processesfor designing semiconductor wafers.

For a firmware and/or software implementation, the methodologies may beimplemented with modules (e.g., procedures, functions, and so on) thatperform the functions described herein. Any machine-readable mediumtangibly embodying instructions may be used in implementing themethodologies described herein. For example, software codes may bestored in a memory and executed by a processor unit. Memory may beimplemented within the processor unit or external to the processor unit.As used herein the term “memory” refers to any type of long term, shortterm, volatile, nonvolatile, or other memory and is not to be limited toany particular type of memory or number of memories, or type of mediaupon which memory is stored.

If implemented in firmware and/or software, the functions may be storedas one or more instructions or code on a computer-readable medium.Examples include computer-readable media encoded with a data structureand computer-readable media encoded with a computer program.Computer-readable media includes physical computer storage media. Astorage medium may be any available medium that can be accessed by acomputer. By way of example, and not limitation, such computer-readablemedia can comprise RAM, ROM, EEPROM, CD-ROM or other optical diskstorage, magnetic disk storage or other magnetic storage devices, or anyother medium that can be used to store desired program code in the formof instructions or data structures and that can be accessed by acomputer; disk and disc, as used herein, includes compact disc (CD),laser disc, optical disc, digital versatile disc (DVD), floppy disk andBlu-ray disc where disks usually reproduce data magnetically, whilediscs reproduce data optically with lasers. Combinations of the aboveshould also be included within the scope of computer-readable media.

In addition to storage on computer readable medium, instructions and/ordata may be provided as signals on transmission media included in acommunication apparatus. For example, a communication apparatus mayinclude a transceiver having signals indicative of instructions anddata. The instructions and data are configured to cause one or moreprocessors to implement the functions outlined in the claims.

Although specific circuitry has been set forth, it will be appreciatedby those skilled in the art that not all of the disclosed circuitry isspecified to practice the disclosure. Moreover, certain well knowncircuits have not been described, to maintain focus on the disclosure.Similarly, although the description refers to logical “0” and logical“1” in certain locations, one skilled in the art appreciates that thelogical values can be switched, with the remainder of the circuitadjusted accordingly, without affecting operation of the presentdisclosure.

Although the present disclosure and its advantages have been describedin detail, it should be understood that various changes, substitutionsand alterations can be made herein without departing from the technologyof the disclosure as defined by the appended claims. Moreover, the scopeof the present application is not intended to be limited to theparticular aspects of the process, machine, manufacture, and compositionof matter, means, methods and steps described in the specification. Asone of ordinary skill in the art will readily appreciate from thedisclosure, processes, machines, manufacture, compositions of matter,means, methods, or steps, presently existing or later to be developedthat perform substantially the same function or achieve substantiallythe same result as the corresponding aspects described herein may beutilized according to the present disclosure. Accordingly, the appendedclaims are intended to include within their scope such processes,machines, manufacture, compositions of matter, means, methods, or steps.

The previous description is provided to enable any person skilled in theart to practice the various aspects described herein. Variousmodifications to these aspects will be readily apparent to those skilledin the art, and the generic principles defined herein may be applied toother aspects. Thus, the claims are not intended to be limited to theaspects shown herein, but is to be accorded the full scope consistentwith the language of the claims, in which reference to an element in thesingular is not intended to mean “one and only one” unless specificallyso stated, but rather “one or more.” Unless specifically statedotherwise, the term “some” refers to one or more. A phrase referring to“at least one of” a list of items refers to any combination of thoseitems, including single members. As an example, “at least one of: a, b,or c” is intended to cover: a; b; c; a and b; a and c; b and c; and a, band c. All structural and functional equivalents to the elements of thevarious aspects described throughout this disclosure that are known orlater come to be known to those of ordinary skill in the art areexpressly incorporated herein by reference and are intended to beencompassed by the claims. Moreover, nothing disclosed herein isintended to be dedicated to the public regardless of whether suchdisclosure is explicitly recited in the claims. No claim element is tobe construed under the provisions of 35 U.S.C. §112, sixth paragraph,unless the element is expressly recited using the phrase “means for” or,in the case of a method claim, the element is recited using the phrase“step for.”

What is claimed is:
 1. A method of making a semiconductor device,comprising: patterning a first portion of a feature and a second portionof the feature separated by a first predetermined distance; andpatterning the first portion with a cut mask to form a first sub-portionand a second sub-portion, in which a dimension of the first sub-portionis less than the dimension of a second predetermined distance.
 2. Themethod of claim 1, in which the first predetermined distance is one of aline tip to tip space and a line space.
 3. The method of claim 2, inwhich the second predetermined distance is a line length resolution of alithographic process having a specified width resolution.
 4. The methodof claim 1, further comprising depositing conductive material on thefirst sub-portion and the second sub-portion to form contact structures.5. The method of claim 1, in which the feature is a local interconnect.6. The method of claim 1, in which the first predetermined distance is alithographic resolution of a first mask used to pattern the firstportion and the second portion.
 7. The method of claim 6, in which thesecond predetermined distance is the lithographic resolution of a secondmask used to pattern the first sub-portion and the second sub-portion.8. The method of claim 1, in which patterning the first portion with thecut mask further comprises etching the first portion into the firstsub-portion and the second sub-portion.
 9. The method of claim 1,further comprising integrating the semiconductor device into a mobilephone, a set top box, a music player, a video player, an entertainmentunit, a navigation device, a computer, a hand-held personalcommunication systems (PCS) unit, a portable data unit, and/or a fixedlocation data unit.
 10. A computer program product configured for makinga semiconductor device, the computer program product comprising: anon-transitory computer-readable medium having non-transitory programcode recorded thereon, the non-transitory program code comprising:program code to pattern a first portion of a feature and a secondportion of the feature separated by a first predetermined distance; andprogram code to pattern the first portion with a cut mask to form afirst sub-portion and a second sub-portion in which a dimension of thefirst sub-portion is less than the dimension of a second predetermineddistance.
 11. The computer program product of claim 10, furthercomprising program code to deposit conductive material on the firstsub-portion and the second sub-portion to form contact structures. 12.The computer program product of claim 10, in which the firstpredetermined distance is one of a line tip to tip space and a linespace.
 13. The computer program product of claim 12, in which the secondpredetermined distance is a line length resolution of a lithographicprocess having a specified width resolution.
 14. The computer programproduct of claim 10, integrated into a mobile phone, a set top box, amusic player, a video player, an entertainment unit, a navigationdevice, a computer, a hand-held personal communication systems (PCS)unit, a portable data unit, and/or a fixed location data unit.
 15. Anapparatus for making a semiconductor device, comprising: means forpatterning a first portion of a feature and a second portion of thefeature separated by a first predetermined distance; and means forpatterning the first portion to form a first sub-portion and a secondsub-portion, in which a dimension of the first sub-portion is less thanthe dimension of a second predetermined distance.
 16. The apparatus ofclaim 15, in which the first predetermined distance is one of a line tipto tip space and a line space.
 17. The apparatus of claim 16, in whichthe second predetermined distance is a line length resolution of alithographic process having a specified width resolution.
 18. Theapparatus of claim 15, further comprising means for depositingconductive material on the first sub-portion and the second sub-portionto form contact structures.
 19. The apparatus of claim 15, in which thefeature is a local interconnect.
 20. The apparatus of claim 15, in whichthe first predetermined distance is a lithographic resolution of a firstmask used to pattern the first portion and the second portion.
 21. Theapparatus of claim 20, in which the second predetermined distance is thelithographic resolution of a second mask used to pattern the firstsub-portion and the second sub-portion.
 22. The apparatus of claim 15,in which means for patterning the first portion further comprises meansfor etching the first portion into the first sub-portion and the secondsub-portion.
 23. The apparatus of claim 15, integrated into a mobilephone, a set top box, a music player, a video player, an entertainmentunit, a navigation device, a computer, a hand-held personalcommunication systems (PCS) unit, a portable data unit, and/or a fixedlocation data unit.